The present invention relates, in general, to chemical mechanical planarization (CMP) tools, and more particularly, to a wafer carrier.
Chemical mechanical planarization (also referred to as chemical mechanical polishing) is a proven process in the manufacture of advanced integrated circuits. CMP is used in almost all stages of semiconductor device fabrication. For example, chemical mechanical planarization allows the creation of finer structures via local planarization and for global wafer planarization to produce high density vias and interconnect layers. Materials that undergo CMP in an integrated circuit manufacturing process include single and polycrystalline silicon, oxides, nitrides, polyimides, aluminum, tungsten, and copper.
In general, the planarity of the starting wafer worsens during manufacturing processes such as material removal steps and various deposition steps. Typically, during the chemical mechanical planarization process, material is removed from the edge of the semiconductor wafer at a rate that is different from the removal rate at the center due to slurry transport effects. This phenomenon, as well as several others including clamp ring marks, can result in edge exclusion. Edge exclusion can significantly reduce yields by rendering die near the edges of a semiconductor wafer unusable. The edge die can make up a large percentage of the overall die on a semiconductor wafer due to the large annular area involved. The yield impact increases as the industry moves to the next generation 300 millimeter diameter semiconductor wafers.
One factor affecting the rate of material removal is the movement of new slurry added to the surface of the wafer and the removal of spent slurry. The slurry transport varies across the semiconductor wafer from the edge to center. More specifically, slurry is removed and replaced at a slower rate at the center of the semiconductor wafer than at the edge. An example of how non-planarity can affect performance of a semiconductor device is illustrated in a copper CMP process. A non-planar die surface in an after-copper polish step results in non-uniform copper interconnect thickness. The non-uniformity of the copper interconnect corresponds to variation in resistance of the interconnect that will directly impact chip performance. In many cases, interconnect delay has become more significant than device delay in the performance of a chip such as a microprocessor.
Accordingly, it would be advantageous to have a chemical mechanical planarization tool that can compensate for different planarization or removal rates in different locations on a semiconductor wafer. More specifically, compensating for different planarization or removal rates will provide increased planarity and uniform material removal rate across a semiconductor wafer. In the limit, the CMP tool and process could be used to reengineer wafers that are out of specification for planarity due, for example, to wafer fabrication tolerances or deposition process variations, through a replanarization process mapped to compensate for the variation in thickness across the out of specification wafer.